1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to transistors having strained channel regions by using an embedded strained semiconductor material within the active region to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Modern integrated circuits typically comprise a great number of circuit elements on a given chip area, which are positioned and connected to each other according to a specified circuit layout. Transistors as active elements, i.e., as circuit elements enabling signal amplification and signal switching, represent one of the dominant components of an integrated circuit, and therefore the overall performance of integrated circuits is significantly determined by the performance characteristics of the individual transistor elements. The operational behavior of the transistors in turn may depend on the overall dimensions, the basic transistor configuration, the manufacturing techniques used and the like. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of field effect transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor or field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region per unit length substantially determines the performance of the MOS transistors. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity per unit length in the transistor width direction, renders the channel length a dominant design criterion for accomplishing an increase in the operating speed of the individual transistors and thus of the entire integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith, such as reduced controllability of the channel, also referred to as short channel effects, and the like, that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. Since the continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques, for example, for compensating for short channel effects, it has been proposed to also enhance the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node while avoiding or at least postponing many of the problems encountered with the process adaptations associated with device scaling.
One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, for a standard crystallographic orientation of the basic silicon layer, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. On the other hand, the creation of tensile strain in the channel region of an N-channel transistor may increase electron mobility. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach for further device generations, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
Therefore, in some approaches, the hole mobility of PMOS transistors is enhanced by forming a strained silicon/germanium layer in the drain and source regions of the transistors, wherein the compressively strained drain and source regions create uniaxial strain in the adjacent silicon channel region. To this end, the drain and source extension regions of the PMOS transistors are formed on the basis of ion implantation. Thereafter, respective sidewall spacers are formed at the gate electrode as required for the definition of the deep drain and source junctions and the metal silicide in a later manufacturing stage. Prior to the formation of the deep drain and source junctions, these regions are selectively recessed based on the sidewall spacers, while the NMOS transistors are masked. Subsequently, a highly in situ doped or an intrinsic silicon/germanium layer is selectively formed in the PMOS transistor by epitaxial growth techniques. Since the natural lattice spacing of silicon/germanium is greater than that of silicon, the epitaxially grown silicon/germanium layer, adopting the lattice spacing of the silicon, is grown under compressive strain, which is efficiently transferred to the channel region, thereby compressively straining the silicon therein. This integration scenario results in a significant performance gain of the P-channel transistors. Hence, a similar concept has been proposed for N-channel transistors by using a silicon/carbon material that has a smaller lattice spacing compared to silicon.
Although the incorporation of a silicon/carbon alloy may be a promising approach for enhancing performance of N-channel transistors on the basis of an embedded strain-inducing semiconductor material, conventional techniques may result in a less pronounced performance gain for transistor architectures requiring shallow drain and source regions, at least in the vicinity of the channel region. That is, the incorporation of the required dopant species by ion implantation may result in significant lattice damage, which may result in a significantly reduced strained lattice after re-crystallization on the basis of anneal processes, since a significantly reduced degree of carbon atoms may be positioned at the lattice sites. Consequently, forming the shallow drain and source regions, which may also be referred to as extension regions, by ion implantation may result in a significantly reduced strain component in the adjacent silicon channel region. On the other hand, the incorporation of the dopant species during the epitaxial growth process according to well-established conventional deposition techniques may lead to a reduced strain-inducing mechanism caused by a shallow cavity or an increased offset of the shallow in situ doped drain and source extension regions, as will be explained in more detail with reference to FIGS. 1a-1b. 
FIG. 1a schematically illustrates a cross-sectional view of an advanced transistor element 100 at an early manufacturing stage when providing a silicon/carbon semiconductor alloy adjacent to a silicon-containing channel region. The transistor 100 may comprise a substrate 101, which may typically represent a silicon material, possibly in combination with a buried insulating material (not shown), above which is formed a silicon layer 103. Furthermore, the transistor 100 may comprise a gate electrode structure 105, which may comprise, in this manufacturing stage, a gate electrode material 105C formed on a gate insulation layer 105D, which separates the gate electrode material 105C from a channel region 106 of the transistor 100. Moreover, the gate electrode structure 105 comprises a silicon nitride cap layer 105A and a sidewall spacer structure 105B, for instance comprised of silicon nitride. Furthermore, the transistor 100 is exposed to an etch ambient 107, the process parameters of which may be adjusted so as to obtain a substantially anisotropic etch behavior for forming cavities 104 laterally adjacent to the gate electrode structure 105. Generally, a lateral offset of the cavities 104 from the gate electrode material 105C may be determined by the width of the spacer structure 105B and the parameters of the etch process 107. Generally, selecting a moderately small lateral offset may be advantageous with respect to closely positioning a strain-inducing semiconductor alloy to the channel region 106. Furthermore, a depth of the cavity 104 may also have a significant influence on the overall performance gain obtained by the strain-inducing silicon/carbon material to be filled into the cavities 104 in a later manufacturing stage. That is, providing an increased depth for the cavities 104 may result in an overall increased strain component in the channel region 106 for a given composition of the silicon/carbon material to be filled in.
FIG. 1b schematically illustrates the transistor 100 in a further advanced manufacturing stage. As shown, the transistor 100 is exposed to a deposition ambient 108, in which process parameters, such as carrier gas flow rate, precursor gas flow rate, pressure, temperature and the like, are selected such that the silicon/carbon material may preferably be deposited on exposed crystalline silicon areas, while a significant deposition of silicon/carbon material on other areas, such as the cap layer 105A and the spacer structure 105B may be significantly reduced. A corresponding well-established deposition process may frequently be referred to as a selective epitaxial growth technique, in which a crystal structure may grow on exposed surface portions of the silicon layer 103, which may act as a template material for the crystalline growth of the silicon/carbon material. During the selective epitaxial growth process 108 according to conventional strategies, the deposition of the silicon/carbon material may occur in a substantially “conformal” manner, thereby forming layer after layer, as is indicated in FIG. 1b, in which a strained silicon carbon material 109 may be considered as being grown in the form of a plurality of individual sub-layers 109A . . . 109N. Hence, a similar growth rate may occur in the horizontal and vertical directions during the deposition of the silicon/carbon material 109.
The transistor 100 as shown in FIGS. 1a-1b may be formed on the basis of well-established process techniques, which may involve the formation of a gate insulation material followed by the deposition of an appropriate gate electrode material, such as the materials 105D, 105C, possibly in combination with the deposition of the cap layer 105A. Thereafter, these material layers may be patterned on the basis of sophisticated photolithography and etch techniques. Next, the spacer structure 105B may be formed by depositing a silicon nitride material and anisotropically etching the same in order to obtain the structure 105B as shown. Thereafter, the etch process 107 may be performed by using appropriate process parameters, as previously discussed, in order to obtain the cavities 104 extending down to a specified depth. Thereafter, appropriate cleaning recipes may be used, for instance on the basis of well-established wet chemical chemistries, in order to remove contaminants created during the preceding manufacturing steps. Thereafter, the deposition process 108 may be performed by using appropriate process parameters as discussed above, thereby forming the silicon/carbon material 109. As previously indicated, the deposition behavior during the process 108 may substantially not allow the desired high degree of flexibility in designing the overall transistor characteristics of the device 100. That is, if an overall high strain component may be desired in the channel region 106, the cavity 104 has to be formed to extend deep into the semiconductor layer 103 so as to obtain a moderately large amount of strain-inducing material in the form of the silicon/carbon alloy 109. On the other hand, if shallow drain and source extensions are required, an in situ doping during the deposition process 108 may have to be delayed until a final phase of the deposition process 108, thereby, however, also resulting in a significant lateral offset of the corresponding in situ doped silicon/carbon material. For example, as shown in FIG. 1b, it may be assumed that at a deposition phase corresponding to the layer 109N, an appropriate precursor material comprising an N-type dopant species may be introduced into the deposition ambient of the process 108. Consequently, a lateral offset 109Z may be obtained for the highly doped silicon/carbon material 109 starting from the “layer” 109N, which may substantially correspond to the desired depth of a corresponding shallow drain and source extension region. On the other hand, positioning the shallow in situ doped material 109N closer to the channel region 106 may require the cavities 104 to be formed with a reduced depth, which on the other hand may result in a reduced amount of strain-inducing material and thus in a reduced strain component in the channel region 106. In some conventional approaches, the silicon/carbon material 109 may be provided in a substantially non-doped form and the corresponding shallow drain and source regions may be formed by ion implantation, thereby, however, providing a significant strain relaxation in the shallow drain and source regions, which may thus also result in a reduced overall strain component.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.